Believing the Hype(r-V)

An update on my Hyper-V adventures:

I tore it all apart and rebuilt to clean up my mistakes from the first time around, and it is much simpler this time.  Here's a rough set of steps:

  1. Make sure you have a working Windows domain first (2012 is preferable, but 2008+ works)
  2. It's best to have one Windows Server 2012 machine to administer everything from.
  3. Boot the host from the DVD you built, and install onto the local storage.  At this point it's better if any external storage is disabled
  4. After the reboots, log in, set up one NIC and join the domain
  5. Install MPIO if required
  6. Attach the external storage if required
  7. Use the Storage manager to configure it.  There's another post coming on why you don't need DISKPART anymore
  8. Tell Hyper-V how to use the extra storage
  9. Create a Virtual Switch to connect to the outside network
  10. Go virtualise something.
Next time, we'll dive more into the intricacies of the Hyper-V universe

FreeBSD, IBM x-Series and UEFI

FreeBSD, IBM x-Series and UEFI

I banged my head on the rack for quite a while getting an x3250M3 to boot FreeBSD 9.1 recently, and I thought I would share what I learned.

I am using the standard LSI Logic RAID controller (mpt device) with a pair of mirrored 500GB SATA drives.  Ultimately I intend to attach it to a DS4700 array I have lying around in the lab as well, but that's a topic for another post.
So we could boot from the Mylex controller, it is essential that you enable "legacy" boot in the boot manager

I could boot from the 9.1 (AMD64) DVD and everything would install just fine.  When I rebooted, the system would just hang.  Oddly enough, I could boot NetBSD from the same machine, so what was the difference?

Probably a lot, but then I stumbled across a FreeBSD UEFI WIKI, which had the following gem:

"Partitions not seen. When using GPT, FreeBSD will create a protective MBR. This MBR has one partition entry covering the whole disk. FreeBSD marks this partition active. This causes at least some UEFI implementations to ignore the GPT. To fix this the partition needs to be marked inactive"

I realise we're not trying to install any EFI component, but it was worth a try.  After failing to fix the partition record, I took another approach and just reinstalled with a standard MBR partition table, INSTEAD of the GPT partition entry.

Boots just fine after that.

OK Hyper-V, it's time to put up or shut up

Believe the Hype(r-V)?

I run a modest-sized VMWare shop, and we just went through the exercise of moving to VSphere 5.1, so why am I writing about Microsoft's Hyper-V Server 2012?

Mostly because I can.  More and more people I meet these days are coming back to look at Hyper-V.  It hasn't been "quite there" up till now, but by all reports in it's 2012 incarnation, there is much to recommend it.

Firstly, the licensing:

Hyper-V Server 2012 is a free download from Microsoft.  OK, so is VMWare or Xen, but Microsoft have effectively uncoupled Hyper-V and Windows.  But you'd better like PowerShell, because that's all you get out of the box to manage it.  And like ESXi, about all you can do is to complete the basic setup.

Hardware offload of IPSec:
For us, this is pretty important.  We use IPSec heavily, and it's a pig within a VM.  Hyper-V lets me offload this task from the guest to the physical hardware in the system (I'm speculating how that's even possible), and this should at least give us a usable performance boost.  More news as it comes to hand.

Port Mirroring in the virtual switch:
This is worth the price of admission alone.  Now I can capture traffic that never hits a physical port.  Great for application development.

Getting it going

It doesn't get much easier than this.  Download, burn an ISO and boot.  But then what to do?  Well, you can set the hostname, and IP address.  But oddly, from the menu, you can't manually assign an IPV6 address to the machine.  Or did I miss something?

Great, so how do you manage it?  In the old days, you'd bring up Hyper-V Manager.  But as this is a cut-down server core installation (and remember, Server Core is cut waaaay down to start with), there's no straightforward way to do it from the console.  Search for KB958830 to get the management tools to execute on a different machine.  Just like the other guys.

But you also need to enable remote management on the Hyper-V server with the script HVRemote.wsf Why that's not included I am not too sure

You'll also find this article useful if you're installing the tools on Windows 8.  Seems Windows 7 doesn't work so well.

I gave up and used an MSDN release of Server 2012.  Everything just worked after that.  So while the hypervisor itself might be free, a platform to manage it is not.


I had an IBM DS4700 and some fibre cards lying around in the lab (no, really I did...) so I guessed that might be pretty useful if I set up a 1TB LUN for Hyper-V to use.  Once again, technet comes to you aid, because you need to add the MultiPath I/O modules  and from Server Core, it's a little more challenging, at least when it comes to IBM Storage.  This is one area where VMWare has it all over the competition.  Multipath I/O is somehow native in the system and needs little if any intervention.  On Windows or standard Linux/FreeBSD it's a mess.  FYI, Solaris gets much closer to plug and play, but we're not discussing that just now.

Next problem I had was when I presented up the LUN, it was read-only.  Fortunately this is a known situation, and the fix is well documented by Microsoft in KB971436.  But I'll summarise it here for you.

SAN Policy brings all new volumes into the system as "Offline" and "Read-Only".  The solution is

  1. Start up DISKPART and do a LIST DISK.
  2. Select the disk you want to change (it will show "Offline")
  3. SELECT DISK <#>
  5. DETAIL DISK.  Look for Read-only: Yes
There, you should be good to go.

Forward To The Past - 6

How are we going to power this thing?

To start with, I have been using a bench power supply.  This is a very nice device, but not a good long-term solution.

When the project is finished, I will most likely use a Jaycar MP3486 5V regulated plugpack.  These devices retail for around $A20 I don't think it's worth even designing a power supply.  We need only a single 5V rail and this supply has a 1.5A capacity which should be sufficient.

If it's not enough, there is the MP3480 with a 3A rating.

You might need to be a little forceful to use the latter with a breadboard however, because of the wire gauge.

Forward To The Past - 5

Single Stepping

So far, there's no reason why things should not just work.  But what if there's a problem?  Last night I was trying to work out why one of my address outputs didn't work right, and it occurred to me that since the Z80 is essentially a static processor, it would be pretty easy to add a single-step clock to our design so far.

All this requires is a 74LS00 a Single-Pole Double-Throw (SPST) pushbutton switch and a couple of resistors.  Now, for each push of the switch we get one clock transition. 

I will update the main schematic soon to reflect this change, and provide a way of selecting either option without rewiring, but since I'm working on breadboards, this is not too big a challenge to change over at the moment.

Another option would be to use a very low speed clock.  We could either have a separate RC oscillator, or divide down the 8MHz signal to pretty much anything we like.

What would you rather see?

Forward To The Past - 4

Well Buffer Me...

Having got our CPU up and running (sort of), the next step is to complete most of the core circuitry around the CPU.

Historically, microprocessors were pretty fragile devices, and had a very limited fanout capability. That is, the ability to drive a number of integrated circuit inputs from it's output pins.  The solution is to add a driver or "buffer" device between the CPU and anything it needs to talk to.

I will concede it isn't strictly necessary in our design but since I don't know what I am going to be connecting this device to in the future, better to start with a solid foundation. Right?

One, Zero and Huh?

But it gets a little more complicated, and I think we need to dive into some theory.  If you're an old hand feel free to skip ahead.

Still here?  Good...

We know there are two logic states High and Low (or 1 and 0 if you prefer) and we also know that multiple devices can't share the same wire in a simple circuit because the High (+5V) and the Low (0V) would not coexist.  But snce we will have memory (more than one chip) and I/O sharing the address and data lines, how are we going to do it?

The answer is known as "Tri-State Logic".  In Tri-State mode, the output of the chip is effectively not connected to the pin.  The reality is somewhat more complicated than that, but for our purposes we can run with this assumption.

The last few paragraphs were a long-winded way of saying we need to use Tri-State buffer chips between the CPU and just about anything it wants to connect with.  For the output lines (Address and Status) we will use three 74LS244 Octal Buffer devices.  When the /ENABLE pins on these devices are High the outputs enter a Tri-State condition and the CPU is isolated from the bus.

One-Way Traffic

It's even more complicated yet however.  The Address and Status lines from the microprocessor are straightforward, they are outputs.  We can just buffer the signal and we're done.  But the Data lines are more complicated, because they are bi-directional.  These pins can be inputs or outputs.  Fortunately, there is the 74LS245 Octal Transceiver.  You could also use a pair of 74LS244's if you wanted, but you'd increase the complexity for no measurable gain.

But how do you control it all?

So now we have everything buffered up, but how do we know when to turn buffer outputs on and off, or set the direction of a transceiver?  The Z80 CPU does almost all of it for us.  Overall output control is generated by using the /BUSACK signal.  When a device wants to take control of the address and data busses, it will assert (drive Low) the /BUSREQ line.  When the CPU is ready to grant control, it will assert /BUSACK.  We can use /BUSACK to control the buffer devices in the following way.  When /BUSACK is NOT asserted (High) we know the Z80 is in control and our buffers should be output enabled.  But the /G line on the buffers needs to be Low to enable the outputs, so we use a 74LS04 inverter to reverse the signal for us.

Similarly, when /DIR is asserted (driven Low), data flow from the "A" side of the 74LS245 to the "B" side.  Since our "A" is connected to the Z80, /DIR means we are writing data.  We can simply use the /WR line from the Z80 to achieve this.

Last Steps

We still don't have any memory yet (don't worry,we will get there!), so in order to test our work we will use the same trick as last time.  Tie all the data lines Low.  When you fire it up, you will see logic low on the CPU pins for the data and the buffered address lines will count out via the 74LS244's

Parts List So Far

U1:    Z80B CPU
U2:    74LS244 Octal Buffer
U3:    74LS244 Octal Buffer
U4:    74LS245 Octal Transceiver
U5:    74LS04 Hex Inverter
U6:    74LS244 Octal Buffer
O1:    6MHZ Oscillator
C1:    0.1uF/10VW ceramic or monolithic capacitor
C2:    0.1uF/10VW ceramic or monolithic capacitor
C3:    0.1uF/10VW ceramic or monolithic capacitor
C4:    0.1uF/10VW ceramic or monolithic capacitor
C5:    0.1uF/10VW ceramic or monolithic capacitor

Forward To The Past - 3

One tiny victory tonight:

If you tie all the data lines of a Z80 CPU low, then tie RST, BUSREQ, WAIT, INT and NMI high and apply a clock you get a rather large 16-bit counter.  Using an oscilloscope or even a fast logic probe, you will see the address lines cycling through

Why?  Well opcode 00 is NOP (No Operation), so the address counter just moves on to the next address.  Other useful signs of life will be:

/MREQ and /RD will be low (we're reading memory) while /IOREQ and /WR will be high.  HLT will also be high.

I would also recommend using a packaged crystal oscillator, as it's just one less thing to have to get working.

So for our first test, the wiring will be:

Pin  Signal  Tie-to
16   /INT         +5
17  /NMI         +5
24  /WAIT      +5
25  /BUSREQ +5
26  /RST          +5
  7  D4              GND
  8  D3              GND
  9  D5              GND
10  D6              GND
12  D2              GND
13  D7              GND
14  D0              GND
15  D1              GND

11 VCC           +5V
29 GND           GND

Here's a schematic for this simple stage.  Note that the schematic assumes a 14 pin oscillator, whereas the photo shows an 8-pin device.  The layout of the device is the same however.

Foward to the past - 2

Foward to the past - 2

Almost everything arrived just moments ago from Element 14.  By "almost everything", the only thing missing is the Z85C300 SIO chip.  But I can make a start without it I hope.

Foward to the past

OK, I admit it I am a bit old when it comes to the technology business.  I built my first "computer" such that it was in 1977 when I was thirteen years old.  I still have it in a box someplace too.

So this started out as an exercise to show my kids (whom I love dearly, but see computers simply as commodities) just what is involved.  Before you all think I am a complete sadist one is studying mechatronic engineering, and another wants to work in IT when he finishes school.  (There's also an architect and a three year old who wants to be a doctor, but I digress)

The plan was pretty simple.  Build a functional Z80 system from scratch.  Simple in principle, and hopefully execution as well.  When I mapped out the task I came up with the following:

  1. Create a simple design, based on datasheets.  Processor, RAM, ROM, Serial and Parallel I/O
  2. Get all the parts together
  3. Assemble it on a set of breadboards
  4. Write a simple monitor ROM
  5. Find something meaningful for it to do when I'm finished
After about a week of mucking about I have come up with a 12-chip design that will do everything I wanted.  I could cut it back to 8 by eliminating the buffers for the CPU, but then I may want to connect it to something bigger next time, so better to start as we mean to go on.

The biggest complication so far was that 64Kx8 SRAM is almost impossible to  find these days, so I decided to use a 128Kx8 (AS6C1008) and just tie A16 down.  There's no attempt to do bank select or anything so esoteric at this stage.

I also allowed for a 32Kx8 EPROM and have built in full address decoding and switching so I can take this out of the address space if I want to try and implement CP/M or similar in the future.  The MicroBee did this years ago, and while I didn't copy their schematics I hope the designers don't mind me borrowing the design.

I will post the schematic here shortly, once I export it from my design package.  Feel free to use some or all of it for any non-commercial purpose.

Wasting your and my time

I had a really interesting experience recently which I hope might enlighten others as much as it did me: I was approached (via LinkedIn) by ...